1. Field of the Invention
The present invention relates to a digital-to-analog converter (hereinafter referred to also as D-A converter in abridgement) for converting a digital signal into a corresponding analog signal.
2. Description of the Prior Art
In order to have a better understanding of the invention, description will be first made with respect to a hitherto known D-A converter with reference to FIG. 1 which is a block diagram showing a typical example of the prior art D-A converter of the pulse width modulation (PWM) type. For simplification of this description, it is assumed that each of the values of digital data to be convered into a corresponding analog quantity consists of four bits and thus the counter used for the conversion is also of four-bit capacity. In FIG. 1, reference numeral 1 denotes a clock pulse generator circuit for producing clock pulses which are counted by a counter 2 having a carry output C. All the bits of digital data D.sub.1, D.sub.2, D.sub.3 and D.sub.4 fed to digital input terminals 4a, 4b, 4c and 4d, respectively, are compared with all of the bits of the outputs Q.sub.4, Q.sub.3, Q.sub.2 and Q.sub.1 of the counter 2 through a comparator circuit 3. When coincidence is found, the comparator circuit 3 will produce a coincidence signal. An RS flip-flop 5 has a set input terminal S connected to the carry output terminal C of the counter 2 and a reset input terminal R connected to the output terminal of the comparator circuit 3 so as to be reset by the coincidence signal output from the comparator 3. The Q-output (non-inverted output) from the RS flip-flop 5 is connected to the input of an integrator circuit 6 to be converted into a corresponding analog signal which in turn is applied to the input of a voltage conversion circuit 7 adapted to produce a corresponding voltage signal at an analog voltage output terminal 8.
Next, the operation and the associated problems of the D-A converter of the prior art arrangement described above will be discussed with the aid of signal waveforms illustrated in the diagram of FIG. 2. The clock pulse generator circuit 1 produces clock pulses such as shown at (a) in FIG. 2, while the counter 2 counts 16 pulses labelled "0" to "15" during a single counting cycle or period. When the contents of the counter 2 becomes "0", the carry-out signal, such as shown at (b) in FIG. 2, is produced and supplied to the set input terminal S of a RS flip-flop 5 as the set signal. Under these conditions, when a digital data input, such as "0101" (which is equal to "5" according to the decimal notation), for example, which is to be converted into an analog quantity is applied to the digital input terminals 4d, 4c, 4b and 4a, then the input data is compared with the contents of the counter 2 by the comparator circuit 3, as result of which the coincidence signal, such as shown at (c) in FIG. 2, is produced at the time when the contents of the counter 2 becomes equal to "5". The coincidence signal is then supplied to the reset input R of the RS flip-flop 5 as a reset signal. Accordingly, the RS flip-flop 5 is set when the contents of the counter 2 is equal to zero and reset when the contents of the counter 2 is equal to "5". Consequently, the Q-output signal from the RS flip-flop 5 will be as shown at (d) in FIG. 2 during a single counting cycle or period of the counter 2. Generation of such a Q-output signal is subsequently repeated for every succeeding counting cycle or period of the counter 2. The Q-output signal is converted into a DC signal by the integrator circuit 6 and finally converted into a corresponding voltage value by the succeeding voltage converter stage 7.
If the number of clock pulses counted by the counter 2 during one period (a single counting cycle) is represented by N, the input data value applied to the input terminals 4d to 4a is represented by n and a reference voltage of the voltage converter circuit 7 is represented by V.sub.O, then the voltage V produced at the analog signal output terminal 8 is given by the following expression: EQU V=n/N.multidot.V.sub.O
This means that the analog output signal voltage as obtained in proportional to the input digital data n.
In the D-A converter as described above, examination will next be made on the operation of the converter at the time when the input digital data value n undergoes variation. Referring to FIG. 3, it is assumed that a change occurs in the digital data value n at a given point in time T in the course of elapse of time t. The analog output voltage will then change during a finite time .DELTA.t, which imposes limits on the system for reasons described below:
So far as t.ltoreq.T, n=n.sub.1, and when T&lt;t, n=n.sub.2, wherein n.sub.1 &lt;n.sub.2. On the above assumption, the Q-output of the RS flip-flop 5 will of course change the waveform thereof at the boundary time T as is shown at (a) in FIG. 3. However, it will be noted that the output analog voltage will not instantly change in a step-like manner because of the time constant of the integrator circuit 6, but a transient delay time .DELTA.t will intervene between the time T and the new steady level of the analog output voltage, as shown at (b) in FIG. 3. Such a delay time .DELTA.t of course depends on the time constant of the integrator circuit 6 which time constant can not however be selected at an arbitrary small value in consideration of the fact that the function of the integrator circuit 6 is to integrate the waveform of the Q-output of the RS flip-flop 5 adequately so that the integrator output is free of any ripple component.
As will be appreciated from the above discussion, the hitherto known D-A converter has been disadvantageous in that the analog output thereof can not follow up a change or variation in the digital input data at a desirable high speed.
In an attempt to overcome the problem described above, there has been proposed a method according to which the digital input data is divided into a first group of more significant bits and a second group of less significant fits with the first data bit group being processed on the basis of pulse duration modulation (PDM), while the second data bit group is processed through pulse rate modulation (PRM). The processed outputs are then mixed together with each other.
The above method is however disadvantageous in that the circuit arrangement for carrying out the method will become necessarily complicated due to use of both PDM and PRM techniques. Besides, in the case of PRM, the number of pulses to be processed provides a critical problem in addition to the difficulty in attaining a stability of the output pulse due to the inherent pulse rise and fall characteristics of this system, as is known in the art.